In footnote #6 you ask which devices are PMOS and which are NMOS. My guess is that the PMOS are at the bottom, so you have a NOR gate.
In typical CMOS processes the PMOS transistors have lower carrier mobility than NMOS transistors. Holes are slower than electrons.
So in standard cells the PMOS transistors are made physically larger to compensate. This helps the device output H->L and L->H transitions be more symmetric.
In typical CMOS processes the PMOS transistors have lower carrier mobility than NMOS transistors. Holes are slower than electrons.
So in standard cells the PMOS transistors are made physically larger to compensate. This helps the device output H->L and L->H transitions be more symmetric.