> IBM calls this "microcode", but it's unclear if this is microcode in the usual sense or just firmware instructions.
IBM had all sorts of unconventional usages of the word "microcode", e.g. parts of the OS/400 operating system were referred to as the "Horizontal and vertical microcode" (they were in fact the kernel of the operating system)
What is the strangest thing you’ve ever seen in a chip? (e.g. has anything ever hinted at either a lucky accident that relied on physical laws that weren’t understood or tech that seemed too advanced to
have been developed by the team that developed it?)
Also- the strange parts of the chip spell DDB, which may be relevant, as the V DDB is mentioned in one of the MAU design patents. Or DDB possibly could be the initials of the team or designers. It could have also served a practical purpose.
I've seen a few things on chips that don't make sense, such as wires to nowhere. Then I figured out that these were bug fixes where they had cut connections.
Chip art is a lot of fun! Years ago when I was working at a startup, we had a wooden statue in the office of a monkey holding a cell phone. Over time he was further accessorized with a hardhat and an official company badge. On one of our prototype tapeouts, we made a not-insignificant effort to render a proper photo of it onto the top layer metal.
The tricky thing was getting multiple colors (shades, really) using what amounts to a single color. Back then, we didn't have any fancy filters like "sketch mode" to turn it into a line drawing, and we were limited to some extent by process design rules for metal size, spacing, density, etc.
We ended up opening the image in GIMP, and converting it to grayscale, then true black and white (1-bit color) by upscaling and using some filter where it preserves the shades by setting the average density of black pixels in an area to match the shade of gray of the pixel in the original. Then we wrote a script that mapped black pixels to solid metal, and white pixels to empty space, on a grid in such a way that all Design Rules were met.
The whole die was a cellular transceiver. If I remember correctly that particular spot happened to be empty on the top layer. Foundries require a minimum density of metal on every layer, so we would have had to put dummy pieces of metal there anyways. We figured why not put a picture
In footnote #6 you ask which devices are PMOS and which are NMOS. My guess is that the PMOS are at the bottom, so you have a NOR gate.
In typical CMOS processes the PMOS transistors have lower carrier mobility than NMOS transistors. Holes are slower than electrons.
So in standard cells the PMOS transistors are made physically larger to compensate. This helps the device output H->L and L->H transitions be more symmetric.
This was another great post. I hope to see you do an Ethernet chip/card post in the future. I had a couple question about the following:
>"The block diagram below shows the complex functionality of the chip. Starting in the upper right, the analog front end circuitry communicates with the ring. The analog front end extracts the clock and data from the network signals."
Do all non-optical network cards have a similar analog circuit as well? Is this generally the transceiver chip on the card?
>"The chip's logic is implemented with a CMOS standard cell library and consists of about 24,000 gates. The idea of standard-cell logic is that each function (such as a NAND gate or latch) has a standard layout."
Are these cell libraries the same as an IP block that you would license today when designing a chip? Did cell libraries become common around the time of this chip?
> Do all non-optical network cards have a similar analog circuit as well? Is this generally the transceiver chip on the card?
Even optical cards have this kind of circuitry in the PHY chip. While the SFP module usually contains surprising amount of logic, most of it has to do with configuration and testing and in the end it is just an pair of LEDs with configurable analog amplifiers.
On the other hand for modern ethernet over TP (1Gbps and up) the analog interface circuitry is significantly more complex (and power hungry), because calling the thing baseband (the "base" in "1000-base-T") somewhat stretches the definition of the word. It uses various line coding and signal processing tricks to squeeze all the bandwith out of the wire.
>"because calling the thing baseband (the "base" in "1000-base-T") somewhat stretches the definition of the word. It uses various line coding and signal processing tricks to squeeze all the bandwith out of the wire."
Interesting. Can you elaborate on why using "base" is a stretch here? I don't think I've heard this before. It's been a while since I've looked at layer 1 but isn't Ethernet just Manchester encoding? What other signal tricks are generally used?
Might you or anyone else have any good resources for Ethernet PHY circuits?
High speed on copper, for networking anyway, has gone all analog now. That's more of a 'broad'-band (in the literal sense) than 'base'-band (in the single frequency, off/on) sense.
Edit:
The Wikipedia page for broadband says it better: "The key difference is that what is typically considered a broadband signal in this sense is a signal that occupies multiple (non-masking, orthogonal) passbands, thus allowing for much higher throughput over a single medium but with additional complexity in the transmitter/receiver circuitry." -- https://en.wikipedia.org/wiki/Broadband
I haven't looked at Ethernet chips in detail, but they have similar analog circuitry. A "PHY" (physical layer) module does the analog encoding and decoding.
Standard cell libraries are lower-level than IP blocks since you're dealing with gates rather than functional units. I'm sure someone here knows about how they are licensed.
On the chip I looked at, the analog module and the CPU were treated as IP blocks. These blocks were built by IBM so the intellectual property itself wasn't an issue. But the blocks were designed by other teams and essentially dropped onto the chip unchanged. For the revised version of the chip, they redesigned the logic but kept the original analog and CPU blocks.
Could the mystery analog loops be impedance matching / baluns? My first thought, the way they stand out bare on the chip, seems similar to other RF magic.
My _guess_ was some sort of (attempt at?) very minor inductance / capacitive correction factor; leaning a bit more towards capacitive for the lack of more loops. In college I tried to do something similar in a term project by using all of the spare surface space on the PCB as a capacitive fill attached to the power supply.
If they were test pads something more like the solder ball or a normal pad might be expected.
