My best advice: synthesize early and often, and spend the time to poke around in the synthesis schematic viewer - Webpack still includes this I believe. It's a great way to compare what you wrote in code to the logic you intended to implement in your mind's eye (or better yet, your notebook).
And read the design guidelines from the FPGA vendor
of the device you are targeting. Xilinx,
Altera (Intel), Microsemi and Cypress all
have different rules for mapping things like
memories, write enables etc.
Xilinx is happy to not reset registers,
Altera will generate a bigger design if
reset is not stated in the code.
Thanks for the advice! I've been synthesizing a bit, fixing a few issues that at least didnt present when building for the simulator. I've yet to run it actually on hardware, though - that part will be fun. Webpack does still come with the schematic viewer, which is really neat.
