Interesting that they converged on a memory/network architecture similar to a rack of GPUs.

- 152 cores per chip, equivalent to ~128 CUDA cores per SM

- per-chip SRAM (20 MB) equivalent to SM high-speed shared memory

- per-board DRAM (96 GB across 48 chips) equivalent to GPU global memory

- boards networked together with something akin to NVLink

I wonder if they use HBM for the DRAM, or do anything like coalescing memory accesses.