Another great article! I always enjoy reading these.
That additional type ‘a’ register, supporting copying directly from the type ‘b’, is intriguing. I can well imagine the article to be correct that it’s a place to stash ESP during interrupt stack setup, specifically if there’s a privilege transition since I would think it’d be easier from an implementation point of view to “simply” copy ESP to that special register, load the new ESP from the TSS, and then stack that special register after stacking SS using the usual stacking logic.
Though of course that then raises the question of how SS itself is handled, since something similar would be needed there I think.
Whatever register is copied has to be one of the "type b" ones - ESP, EBP, ESI or EDI. Only ESP is special enough for the hardware to have that direct path for it.
Maybe it's not (just) for privilege transitions, but automatically saving the value of ESP at the start of every instruction, so that it can be "rolled back" when there is a stack limit violation?
That additional type ‘a’ register, supporting copying directly from the type ‘b’, is intriguing. I can well imagine the article to be correct that it’s a place to stash ESP during interrupt stack setup, specifically if there’s a privilege transition since I would think it’d be easier from an implementation point of view to “simply” copy ESP to that special register, load the new ESP from the TSS, and then stack that special register after stacking SS using the usual stacking logic.
Though of course that then raises the question of how SS itself is handled, since something similar would be needed there I think.