Does this actually work? At some point, and this is been the case for a while, you're limited by thermals. You can't stack more layers without adding more cooling.
He's talking about how they've moved from planar transistors, where layers are just deposited on top of each other, to transisors with increasingly complex 3D structures[1] such as FinFET and Gate-All-Around, the latter having multiple nanowires passing through the gate like an ordered marble cake[2].
There are also cooling and conduction paths taken into account. It was discussed in the design of the xeon version of the i9. Which had me consider clocking down the performance core communication while throttling up the performance cores.
Your sources are excellent. ( Thank you so much for the links. )
Moore's law doesn't say anything about you having to power all your transistors for them to count.
I'm only half-joking: the brain gets a lot of its energy efficiency out of most of its parts not working all that hard most of the time; and we are seeing some glimpses of that in mobile processors, too.
Does this actually work? At some point, and this is been the case for a while, you're limited by thermals. You can't stack more layers without adding more cooling.