Section 3 Building a ARM7 CPU is in my view the best example of this - building a pipelined processor is exactly the sort of thing that sounds impressive, but in truth teaches you exceedingly little for the effort it requires. * Architecture wise, implementing a core in verilog versus simulating it in a higher level language are nearly the same from a learning perspective, there really aren't any special. insights from hardware when just starting out. And doing this in verilog just makes the entire process more obtuse because its hardware. * Microarchitecture wise, a simple pipelined processor teaches you basically nothing about how a modern processor (i.e. superscalar, out-of-order) functions from the perspective of a person higher on the stack. If you were to be using it to springboard to writing an OoO superscalar processor, it would be far better to be given a well-designed multistage core and the assignment be to add pipelining - this avoids the student implementating the multistage core of the processor, which is really mostly straightforward implementation of simple but large state machines, and instead focuses purely on the pitfalls of pipelining while also giving a model of good verilog/processor writing practices.

Another thing which is sortof weird is worrying about the type of RAM - that's getting just way into the weeds of processor design and teaches you nothing except stuff like "how to interface with dual port versus single port RAM blocks". And given the time constraints it makes more sense to just simulate memory anyways.