There's a tiny ROM inside, which just downloads the next stage into SRAM (cpu cache as RAM) from eMMC, SD card or SPI flash, or receives it via UART (XMODEM), according to the state of two GPIOs. This tiny ROM remains accessable, can be dumped and examined.

The next stage is typically u-boot SPL, which then loads a payload of opensbi + u-boot, which in turn loads the device tree and kernel. This is all open source.

There are already alternative boot flows implemented, such as oreboot and tianocore.