> I am assuming (hope I am right!) that the RISC-V board doesn't have the equivalent of the IME on it
Actually, it does! Check the block diagram on the first PDF linked to by this article, it has two RISC-V "monitor cores", a 32-bit one and a 64-bit one, besides the four 64-bit main cores.
> and thus will be open-source "librebootable" from the start, with no binary blobs.
There's always going to be a small bootstrap ROM, to configure everything to the point where code can be loaded from the external flash; but other than that, I agree with you: I also hope that the bootstrap code, and the code which runs on these "monitor cores", will be open-source from the start.
Actually, it does! Check the block diagram on the first PDF linked to by this article, it has two RISC-V "monitor cores", a 32-bit one and a 64-bit one, besides the four 64-bit main cores.
> and thus will be open-source "librebootable" from the start, with no binary blobs.
There's always going to be a small bootstrap ROM, to configure everything to the point where code can be loaded from the external flash; but other than that, I agree with you: I also hope that the bootstrap code, and the code which runs on these "monitor cores", will be open-source from the start.