It's not really a compiler issue tho. SIMD is meant to pointwise map an operation across multiple "lanes" in a single operation. You can't have lane interdependence on the result.

(V)PALIGNR shifts between lanes just fine, but only with byte granularity.

Because of the byte granularity, there's no interdependence between lanes. The result within a lane is not affected by the values of the other lanes.

As it turns out, yes: https://godbolt.org/z/xEqrx5dY4

SSE2 adds the PSRL/PSLL operators, which are basically i128 shift operators on vector registers (i.e., shift continues between lanes), so you can pretty easily map i128 to vector registers if you're only doing and/or/xor/shifts.

No, it doesn't shift across 64-bit boundaries. Take a look at the gcc output in your link ``` movdqa xmm0, XMMWORD PTR [rdi] movdqa xmm1, xmm0 psrlq xmm0, 10 psrldq xmm1, 8 psllq xmm1, 54 por xmm0, xmm1 movdqa xmm1, XMMWORD PTR .LC0[rip] ```

That's a lot of psr and psl instructions for a "single 128-bit wide shift"...

The 128-bit wide shifts PS{L,R}LDQ only have byte granularity. They're a special case of a byte shuffle.

The "Q" at the end is "quadword", so it's 64 bits (8 bytes).

No, you're thinking of PS{R,L}LQ.

On 64 bit computers you've been able to use 128 bit unsigned ints as a gcc extension for a long time now and the bit twiddling stuff works exactly as you'd expect. The relevant types are __int128 / unsigned __int128.

Clang has something similar and my understanding is that c23's _BitInt will let you do this.

Yes, but compilers seem to disagree on whether they use a pair of 64-bit registers, or an SSE register under the hood (reusing link from a reply): https://godbolt.org/z/xEqrx5dY4