Per the AVX10.1 Instruction Set Reference, p. 1-2 (355989-001US rev 1.0)[0], AVX10 support will begin with 6th gen Xeon processors (based on Granite Rapids), which are due next year. Client support is not called out, so your guess of Lunar Lake (late 2024-early 2025) is probably a good guess.
No, the instruction set supported by Lunar Lake has been published by Intel a few months ago and it is almost the same as that of Arrow Lake S, i.e. without AVX10 or AVX-512 support (Arrow Lake S supports more instructions than Arrow Lake, e.g. it has SHA-512 secure hash instructions).
It is likely that Panther Lake, to be launched in 2025, probably in the second half of the year, will be the first Intel CPU supporting the 256-bit subset of the AVX10.2 ISA version.
The 2024 Granite Rapids will probably be the only Intel CPU supporting the AVX10.1 ISA version (with full 512-bit support), because all the following will start from AVX10.2.
AVX10.1 is just Sapphire Rapids' AVX-512 renamed, so arguably SPR (and early Alder Lake) already support AVX10.1, just without declaring the relevant CPUID bits.
Client support depends on E-cores supporting it, and Intel have specified that they'll start with AVX10.2. I don't believe that any core has been announced with AVX10.2 support yet, and we the latest we know is Lunar Lake's ISA support.
Granite Rapids has a few extra AVX-512 instructions (including those added by Tiger Lake, but omitted in Sapphire Rapids and Alder Lake), so Sapphire Rapids does not support all of AVX10.1. Therefore neither Sapphire Rapids nor Emerald Rapids may turn on the AVX10 CPUID bits.
Nevertheless, the differences between the AVX-512 instruction sets of Granite Rapids and Sapphire Rapids are small and of little importance.
I couldn't find any new AVX* instructions added to Granite Rapids (I see PREFETCHI and some AMX additions, neither of which fall under the AVX category), and VP2INTERSECT isn't listed under AVX10 or Granite Rapids.
Nope. In fact, it probably won't be in client until after Lunar Lake (2025+).