This was probably also due to impedance matching between all the lines involved.
Digital signals (when using N/P balanced lines) also have this problem, to a lesser extent. Some CAD EE design software have ways to design squiggly traces to balanced impedances in traces that have to go around corners on the PCB and end up with different lengths.
Digital signals (when using N/P balanced lines) also have this problem, to a lesser extent. Some CAD EE design software have ways to design squiggly traces to balanced impedances in traces that have to go around corners on the PCB and end up with different lengths.