Very nice, and great that cheap PCB fab can now do small enough lines to reach the individual pads of these chips, at least in the outer ring. Some of them are set up so that the inner pads are grounds anyway, so less important. I wonder if affordable PCB fab will get to the point of being able to do vias under the chip, and traces between pads, as is apparently currently possible with expensive boards. I'm not a hardware guy but this stuff always interests me.
Seems like the solder pad for an interior ball could double as the via to an inner PCB layer? Then you only need traces to the outer balls, at the surface.
This is an actual technique used for these small packages! It's called "via in pad." Unfortunately it's not as simple as putting a hole in the pad because during solder reflow, the hole will wick the solder ball away from the chip, causing an open connection and possibly sucking the chip down and causing other pads to fail too.
Proper via-in-pad is a cost adder, because there's an extra step to backfill the vias with metal. Unfortunately it hasn't trickled down to hobbyist 4-layer processes yet.
Couldn't you fill the via with solder with a soldering iron before you place the chip if you're doing a hobbyist 4-layer process? Or do you mean the kind of hobbyist 4-layer process where JLCPCB solders the parts on too?
Hmm, maybe you could. I haven't tried it. You'd need to make sure that both sides of the via are un-tented (no green solder mask) so that the solder would flow through. The via would need to end up flat so the solder ball on the part would stick. And you still might get solder bleeding through when you reflow.
For high-ball-count FPGAs, it sounds super tedious to prep. And obviously it's a no-go for machine assembly. But for smaller stuff it sounds feasible!
It would have to be multiple interior balls since the min via size is larger than the distance between pads. Thus the hope that future cheap board fab can make smaller vias. I also see some parts in 3x3mm QFN packages which is nice and small while still hand workable, but it seems like chip vendors would rather have large numbers of pins. For my own purposes I usually don't want that many and would rather keep the package small.
It doesn't matter if the via size is bigger than the distance between pads, or the ball, if in fact the via does not need to be there. All that does matter is whether the via is bigger than the ball sitting on top of it, and enough so to touch the next ball over.
Note that for mass production, you can't put a 'standard' via directly under a BGA/WCSP ball, as the via will 'suck away' the BGA ball via capillary action. You'd need to ask the board house to plug the via, which likely brings it into the 'expensive' range of things again.
OK, reading more carefully, I see that the actual minimum via diameter on that board process is too big. It is sort of understandable if they need room for the interior plating. That is very tiny!
It is very possible that general availability of chips like this might press the board houses to develop techniques for accessing all the pins. I'm sure that we'll see some competing creative solutions.
I imagine a microvia cut by laser would work quite nicely on three of those pins.
The fourth pin, Vcap, would be frustrating, because using two vias to place a capacitor on the opposite side of the IC is labor-intensive, and using two vias to place a capacitor beside the IC is a bit of an unnecessarily long signal path for a filtering component. I'd rather gouge a hole and solder a capacitor directly onto the IC between Vcc and Vcap, but "gouge a blind hole in the dielectric and solder an 01005 capacitor to the IC" is not a commercially viable answer either.
Maybe pray your design doesn't need Vcap or that this can be tied to GND?
