This project is still a great example of a complete computer design, starting from Niklaus Wirth's own RISC5 CPU (not a RISC-V) and very simple peripherals over the OS, runtime/garbage collector, compiler, GUI and simple example applications.
One problem of the original implementation is that it was based on an old Xilinx Spartan 3 development board. This is not only no longer available, but it is one of the few FPGA boards that used 32 bit wide fast (12 ns IIRC) asynchronous SRAM chips. Wirth's hardware design relies heavily on this.
Shameless plug: my student Rikke's port of Project Oberon to RV32I (this is a real RISC-V), however, we still need to find some time to build an FPGA-based SoC. Currently, it runs in emulation: https://github.com/solbjorg/oberon-riscv
The original implementation of Oberon was based on a Nominal Semidestructor 32032. Thanks for linking these more recent designs! Especially, I had no idea Oberon had been ported to RISC-V, which is very inspiring indeed!
Right, Wirth's group used to build their own machines. The previous Modula-2 machine (Lilith) was a microcoded 16-bit system built from SSI/MSI 74-series TTL components whereas the Ceres family of workstations used different CPUs and support chips from the NS32k family - the final version (Ceres 3) used a low-cost embedded version of the NS32k without an MMU (you don't need one for a type-safe language - that was at least the motivation for this...). It could run diskless and boot over a proprietary network, which used the same hardware (Zilog Z8530 SCC) as Apple's Localtalk in Macs (but a different protocol, I think).
An FPGA reimplementation of the Ceres would be great to have. Someone already did the hard work and implemented a NS32k soft core - http://www.cpu-ns32k.net/index.html
The old edition of the Project Oberon book that described the NS32k version is a bit hard to find. But it's interesting to see how little has changed between the versions.
This should be possible - Hellwig Geisse (forgot to mention his project, sorry - https://github.com/hgeisse/THM-Oberon) is working on an Oberon port to the Terasic DE2-115 FPGA port, which has an Altera FPGA like the MiSTer. The basis of the MiSTer is a Terasic DE10 Nano FPGA board, which has a more recent Cyclone V FPGA (the DE2-115 has a Cyclone II).
On a somewhat different vibe, the Lilith was a pretty interesting machine back then. These FPGA platforms get a lot of attention for retrogaming, but they'd be incredibly interesting for exploring extinct more "serious" hardware platforms.
One problem of the original implementation is that it was based on an old Xilinx Spartan 3 development board. This is not only no longer available, but it is one of the few FPGA boards that used 32 bit wide fast (12 ns IIRC) asynchronous SRAM chips. Wirth's hardware design relies heavily on this.
Some years ago, there was a compatible board, the OberonStation. However, it seems this is no longer manufactured: https://pcper.com/2015/12/meet-the-oberonstation-kid-friendl...
However, some modified designs exist that implement a cache in FPGA block RAM and an SDRAM controller. These can be used with more recent FPGA boards:
- FleaFPGA "Ohm" board with a Lattice ECP5 FPGA and 32 MB RAM (https://fleasystems.com/fleaFPGA_Ohm.html) - https://github.com/Basman74/Oberon_SDRAM
- Radiona ulx3s, another ECP5 in an open source design (https://github.com/emard/oberon) - https://github.com/emard/oberon
- PapilioPro using a Xilinx Spartan 6 LX, another open source PCB design (https://papilio.cc/index.php?n=Papilio.PapilioPro) - https://opencores.org/projects/oberon_sdram
Shameless plug: my student Rikke's port of Project Oberon to RV32I (this is a real RISC-V), however, we still need to find some time to build an FPGA-based SoC. Currently, it runs in emulation: https://github.com/solbjorg/oberon-riscv