Something of note here is the built-in Verilator and Renode simulation. If you don't physically have an FPGA but still want to try custom hardware acceleration this repo lets you simulate your improvements.
> Something of note here is the built-in Verilator and Renode simulation. If you don't physically have an FPGA but still want to try custom hardware acceleration this repo lets you simulate your improvements.
That's pretty cool. Is there any practical limit on the size or complexity of the simulated device?
