I haven't been following the Alder Lake situation too closely, but AVX512 is really multiple things that ought to have been orthogonal: (1) 512-bit vectors, (2) a much cleaner vector instruction set, (3) masked vector instructions.
It's mildly understandable that Intel didn't want to implement (1) on the E cores (though it would arguably have been better to just dual-issue them, like AMD did for 256-bit vectors on the original Zens). But there's no reason not to implement (2) and (3) on the E cores.
Perhaps somebody will clarify that (2) and (3) are available on Alder Lake, that would take a lot of the hurt out of this announcement, but it does sound like they're not -- and that's a major bummer.
> It's mildly understandable that Intel didn't want to implement (1) on the E cores (though it would arguably have been better to just dual-issue them, like AMD did for 256-bit vectors on the original Zens). But there's no reason not to implement (2) and (3) on the E cores.
It is very likely that all these aspects are very hard to separate from each other.
It's mildly understandable that Intel didn't want to implement (1) on the E cores (though it would arguably have been better to just dual-issue them, like AMD did for 256-bit vectors on the original Zens). But there's no reason not to implement (2) and (3) on the E cores.
Perhaps somebody will clarify that (2) and (3) are available on Alder Lake, that would take a lot of the hurt out of this announcement, but it does sound like they're not -- and that's a major bummer.