I don't yet have representative experimental data; the language is designed for the synthesis of synchronous FPGA designs and thus avoids some of the issues Verilog and other HDL suffer from. But it's too early for me to give a recommendation.
> The thing that remains to be seen though is performance benchmarking
Agree. I often use Verilator and I also experiment with LuaJIT (see https://github.com/rochus-keller/LjTools) which is one of the fastest VM available; it intend to use it for HW simulation and debugging too.
Here is the specification: https://inf.ethz.ch/personal/wirth/Lola/index.html
I don't yet have representative experimental data; the language is designed for the synthesis of synchronous FPGA designs and thus avoids some of the issues Verilog and other HDL suffer from. But it's too early for me to give a recommendation.
> The thing that remains to be seen though is performance benchmarking
Agree. I often use Verilator and I also experiment with LuaJIT (see https://github.com/rochus-keller/LjTools) which is one of the fastest VM available; it intend to use it for HW simulation and debugging too.