His point still stands as all the tooling and IPs are the same for FPGA and ASIC and ASIC drives developement of new IPs and tools. FPGA are still the minor market here by far
Place and route tool is different and IPs might use different memory and multiplier macros depending on technology. Serdes transceives will also be different. Ideally this is all hidden from the integrator by parameter selecting technology.
Linting tools, simulation tools, formal verification and synthesis tools are all the same. Verification methodology is also the same.
