You could start by buying an FPGA board, but it will probably sit around for a few weeks while you develop some code to run on it. Instead, you can do an awful lot without having a development board and I suggest getting familiar with the development tools first, with zero $$$ upfront.
Simulation:
ModelSim is the industry-standard simulator and (as someone has already mentioned here), there is a free version on the Intel (was Altera) web site. You will need to sign up to get the download. This version of ModelSim will let you run any design up to a certain number of lines of code, but it's plenty to get started with.
Xilinx Vivado has a built-in simulator, but I have spent most of my career using ModelSim, and I haven't had the need to switch. You also need to sign up to download Vivado; the free version is called Vivado HL WebPACK (Device Limited).
Synthesis and Place/Route:
Synthesis turns your HDL code into a netlist which uses the primitive logic blocks of the FPGA that you're targeting and defines how they are logically connected to each other. Place and Route takes those blocks, finds a place for them to go in the FPGA and tries to connect them up so that the logic delay from one flip-flop (through combinatorial logic + wire delays) to the next flip-flop will meet your target clock speed.
When it comes to seeing what your HDL code will turn into once it's been put into an FPGA, I find that Xilinx have the most advanced FPGA toolchain (Vivado) with some excellent visualisation features for learners. Stay away from Vivado HLS for now; if you want to learn HDL code, the HLS tool is a distraction that won't teach you core HDL design concepts. Vivado does not support Spartan-6 parts; only 7-series and newer.
Using Vivado, take a sample piece of code and try running it through synthesis (don't place/route yet). Look at the result in the schematic viewer. Look at the hierarchy viewer, too. Try to trace a line in the source code to its synthesised result. Once you're happy that you can do this, try running place/route (Run Implementation). You can cross-probe from the schematic view to the chip view and highlight wires and blocks with your choice of bright colours. Take a look at how the schematic primitive blocks end up getting placed and routed in the chip.
Note: If you don't care about connecting up I/O pins in Vivado and you just want to see what a small bit of logic looks like, you can specify "-mode out_of_context" under "Project Manager -> Settings -> Project Settings -> Synthesis -> Options -> More options".
Advanced Stuff:
Anyone can make an FPGA design work at 10MHz or 20MHz, so try something harder. Start off by setting a slow clock speed constraint (50MHz), then try increasing the speed in 50 or 100MHz increments until you hit 300MHz (400MHz or 500MHz if you're adventurous). When does your timing fail? What do you need to do to your logic to make it meet timing?
Text Editor: There's a very nice article choosing a text editor, here: https://www.fpgarelated.com/showarticle/37.php
Simulation: ModelSim is the industry-standard simulator and (as someone has already mentioned here), there is a free version on the Intel (was Altera) web site. You will need to sign up to get the download. This version of ModelSim will let you run any design up to a certain number of lines of code, but it's plenty to get started with.
Xilinx Vivado has a built-in simulator, but I have spent most of my career using ModelSim, and I haven't had the need to switch. You also need to sign up to download Vivado; the free version is called Vivado HL WebPACK (Device Limited).
Synthesis and Place/Route: Synthesis turns your HDL code into a netlist which uses the primitive logic blocks of the FPGA that you're targeting and defines how they are logically connected to each other. Place and Route takes those blocks, finds a place for them to go in the FPGA and tries to connect them up so that the logic delay from one flip-flop (through combinatorial logic + wire delays) to the next flip-flop will meet your target clock speed.
When it comes to seeing what your HDL code will turn into once it's been put into an FPGA, I find that Xilinx have the most advanced FPGA toolchain (Vivado) with some excellent visualisation features for learners. Stay away from Vivado HLS for now; if you want to learn HDL code, the HLS tool is a distraction that won't teach you core HDL design concepts. Vivado does not support Spartan-6 parts; only 7-series and newer.
Using Vivado, take a sample piece of code and try running it through synthesis (don't place/route yet). Look at the result in the schematic viewer. Look at the hierarchy viewer, too. Try to trace a line in the source code to its synthesised result. Once you're happy that you can do this, try running place/route (Run Implementation). You can cross-probe from the schematic view to the chip view and highlight wires and blocks with your choice of bright colours. Take a look at how the schematic primitive blocks end up getting placed and routed in the chip.
Note: If you don't care about connecting up I/O pins in Vivado and you just want to see what a small bit of logic looks like, you can specify "-mode out_of_context" under "Project Manager -> Settings -> Project Settings -> Synthesis -> Options -> More options".
Advanced Stuff: Anyone can make an FPGA design work at 10MHz or 20MHz, so try something harder. Start off by setting a slow clock speed constraint (50MHz), then try increasing the speed in 50 or 100MHz increments until you hit 300MHz (400MHz or 500MHz if you're adventurous). When does your timing fail? What do you need to do to your logic to make it meet timing?