Maybe for personal projects, but I find I spend more time dealing with vivado bugs than I do vhdl bugs. I spent four hours today just getting a simulation to run correctly in 2017.3 upgraded from 2016.1. My Co worker was simultaneously dealing with a bug where deleting a net in ECO was silently deleting other nets, and not necessarily causing an error. EE tools are the worst.
First rule of FPGA development: never ever upgrade IDE in the middle of the project. Even if it’s a move from 2016.x to 2017.y version it can cost 2 months of precious time just dealing with some nonsense migration stuff/broken projects/broken settings.
