That's a big ask. Right now RISC-V has a handful of open source CPU cores. There's no open source network, graphics, peripheral and GPIO hardware that can be cheaply plugged into a synthesized design that can be sold at the price you want. Which is to say, while there's plenty of stuff out there that someone made work on a FPGA once, there's nothing with a track record and validation/driver stack ready that you can throw into your tools and expect to get a working chip with. And that's what those SoCs you find in the Pi and similar boards need if you want to get them out at the small-integer-dollars price point: no-brainer existing IP that won't surprise anyone along the manufacturing and support chain.
> There's no open source network, graphics, peripheral and GPIO hardware that can be cheaply plugged into a synthesized design that can be sold at the price you want.
Why not PCIe? Aren't there already a bunch of design/validation/verification tools for it? A RISC-V CPU with just a bunch of PCIe lanes (and a couple of channels of fast DDR4) coming off of it (and maybe an IOMMU) would be a lot easier to integrate with existing hardware, rather than trying to recreate open-source equivalents of modern GPUs and network hardware.
I like the idea, but unfortunately PCIe isn't easy or cheap to implement on silicon. The problem is that you'd need the PHY, which is the high speed, analog interface, and that needs to be designed and tuned for the fab and process node you're targeting. In practice the only sane way to get PCIe on your chip is to buy a PCIe IP block from Faraday or Synopsys. The same goes for SATA.
Ethernet and USB on the other hand is available in discrete PHY chips, so writing some open-source controller RTL for RGMII and ULPI is much more reasonable for an open-source chip.
(Obviously, if someone would cough up the money for taping out a RISC-V SoC with PCIe PHYs onboard and make it in a large enough volume that the price gets down to reasonable levels, I'd be buying a bunch of'em.)
There are simple open source cores for quite a few IO standards. Some ARM SoCs use Cadence or Synopsys cores.
What could be a good advert for RISC-V would be to design a SoC that used a full featured RV64 main core and simpler RV32I cores as offload engines for each IO device.
