Neural nets are honestly best suited to a ZISC type architecture... In any case, specialized deep learning chips should be on their way.
Not to toot my own horn here, but we're one of the hopeful deep learning chip startups, I'd be happy to answer any more questions or perhaps elaborate on why I think ZISC is better for neural nets.
I don't actually think that the Google TPU is the paragon of deep learning processor architecture, there are a lot of things that I don't think are done very well.
In any case, that being said, the TPU is less of a CISC and much more like a lightweight RISC control mechanism.
I don't really agree. What is labelled a "CISC instruction set" here would more usually just be called a control interface. But maybe I'm missing some sort of context here. (Contrasting it with "ZISC" for marketing purposes?)
It's almost always better to have a dedicated chip implement some algorithm, if it makes economic sense to do so. From hard drive controllers to Google's TPU.
Perhaps it's a confusion of terminology, because most people I know would call it as asip. It has the flexibility to implement any linear operation after all.
Not to toot my own horn here, but we're one of the hopeful deep learning chip startups, I'd be happy to answer any more questions or perhaps elaborate on why I think ZISC is better for neural nets.