I'd agree that most runs are at 90nm or above. Yet, the rest is confusing given I have quite a few papers with competitive stuff done at 45-65nm with some at 28 or 32nm.
So, why you say forget about it or MOSIS below 90nm if academics are getting working chips done that low?
They sign NDAs for the process and get 100-thousand dollar layout packages for academic prices.
If you have a few spare million dollars, you still can't necessarily release a lot of data due to the NDAs - usually they give you models for the processes that are proprietary (and they invested a lot in developing, and so will consider any breach an act of war).
So, why you say forget about it or MOSIS below 90nm if academics are getting working chips done that low?