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https://www-ssl.intel.com/content/www/us/en/processors/archi...

  Volume 3A
  Chapter 9, Processor Management and Initialization
  Table 9-1. IA-32 Processor States Following Power-up, Reset, or INIT
The debug registers are named DR0-3 and will be initialized with 00000000H. I can't find an explicit statement for IA-32e mode (Intel's name for x86_64), but I think it is safe to assume the remaining upper 32 bits will be cleared as well.


and sse regs?




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