"If you don't know what's in the DC, you can't say one way or the other about what it can and can't do."
Sure you can: just go with worst case scenario and assume custom hardware. I did that on Schneier's blog below:
"The room for error here is in the ASIC assessment. We need to figure out how much they can parallelize this, either in cores or custom circuits, in a given ASIC. Then, how many of those can do in one chip at 14-28nm. Then how many they can squeeze in a rack. Then how much factoring can be done with Amazon or Microsoft datacenters full of those. That would be the most paranoid assessment.
You see, the unit prices of these things are really low vs initial development costs. That's one of main drivers for hardware to shrink. The chips might cost pro's $10-30 million to develop with boards a tiny fraction of that. Then, the chips themselves are fabbed dirt-cheap with the boards being inexpensive. If algorithm doesn't need much communication, then they can use standard I/O options to farm out the jobs which then just run until they complete. They could add more capacity year after year cheaply with incremental energy cost after spending a ton of money on chip design and real estate just once. They could get 50,000-100,000 chips with multiple accelerators on each every year.
So, I think the authors upper bound is lower than the real upper bound. Need to get specialists who have implemented algorithms like this in hardware to show how it will likely be implemented. Need at least one person whose done a 28nm design to estimate how much of the chip can be dedicated to that with the other functions considered. Then multiply that by whatever Amazon has to get a decent upper-bound. "
Sure you can: just go with worst case scenario and assume custom hardware. I did that on Schneier's blog below:
"The room for error here is in the ASIC assessment. We need to figure out how much they can parallelize this, either in cores or custom circuits, in a given ASIC. Then, how many of those can do in one chip at 14-28nm. Then how many they can squeeze in a rack. Then how much factoring can be done with Amazon or Microsoft datacenters full of those. That would be the most paranoid assessment.
You see, the unit prices of these things are really low vs initial development costs. That's one of main drivers for hardware to shrink. The chips might cost pro's $10-30 million to develop with boards a tiny fraction of that. Then, the chips themselves are fabbed dirt-cheap with the boards being inexpensive. If algorithm doesn't need much communication, then they can use standard I/O options to farm out the jobs which then just run until they complete. They could add more capacity year after year cheaply with incremental energy cost after spending a ton of money on chip design and real estate just once. They could get 50,000-100,000 chips with multiple accelerators on each every year.
So, I think the authors upper bound is lower than the real upper bound. Need to get specialists who have implemented algorithms like this in hardware to show how it will likely be implemented. Need at least one person whose done a 28nm design to estimate how much of the chip can be dedicated to that with the other functions considered. Then multiply that by whatever Amazon has to get a decent upper-bound. "