Most of the time,

> between the keyboard and the chair

Is where the problem is.

What's the difference between those 4 checkpoints?

From the GitHub's README:

    sd-v1-1.ckpt: 237k steps at resolution 256x256 on laion2B-en. 194k steps at resolution 512x512 on laion-high-resolution (170M examples from LAION-5B with resolution >= 1024x1024).

    sd-v1-2.ckpt: Resumed from sd-v1-1.ckpt. 515k steps at resolution 512x512 on laion-aesthetics v2 5+ (a subset of laion2B-en with estimated aesthetics score > 5.0, and additionally filtered to images with an original size >= 512x512, and an estimated watermark probability < 0.5. The watermark estimate is from the LAION-5B metadata, the aesthetics score is estimated using the LAION-Aesthetics Predictor V2).

    sd-v1-3.ckpt: Resumed from sd-v1-2.ckpt. 195k steps at resolution 512x512 on "laion-aesthetics v2 5+" and 10% dropping of the text-conditioning to improve classifier-free guidance sampling.

    sd-v1-4.ckpt: Resumed from sd-v1-2.ckpt. 225k steps at resolution 512x512 on "laion-aesthetics v2 5+" and 10% dropping of the text-conditioning to improve classifier-free guidance sampling.

Which one is the general use case checkpoint one should be using?

Wow, just checked and Pi 3 is over 100€, and Pi 4 over 200€.

What happened? I remember buying a Pi 3B+ in 2019 for less than 50€.

Apparently also known as the "Baader–Meinhof phenomenon".

Great video, thanks for sharing. I had the same feeling of my palms sweating during some of the shots.

It also sparked my interest for climbing, I'll give it a try for sure (with rope).

Agreed, I stopped reading after this sentence.

Excellent explanation, thanks for sharing!

Is there a known limit for the energy to hash ratio ?

At least "cryptos" in plural is clearly for crypto currencies (I don't think anyone uses "cryptographies").

Yes, the article mentions it:

> What if I have ECC-capable DIMMs?

> Previous work showed that due to the large number of bit flips in current DDR4 devices, ECC cannot provide complete protection against Rowhammer but makes exploitation harder.

It sounds to me like ECC isn't being included in the DDR5 spec due to magnanimity so much as because it doesn't function without it. That ECC has become 'load-bearing'.

Does that mean we need an extended ECC to deal with critical systems that require additional robustness?

Who error checks the error checkers?

It's just a matter of time before someone finds a way to exploit the ECC part, calls it Hammerrow and brings us back to square one...

Rowhamming would be a better pun, as DDR5 uses a Hamming code for error correction.