Project co-creator here - This was something I'd wanted to do since I first started playing with FPGAs 20 years ago but the idea was resurrected during the pandemic. It's definitely easier with an FPGA but there are other projects that interface an ESP32 or RP2040 to the Apple II bus. The FPGA approach allows you to architect your logic in ways that are much closer aligned to the original hardware design and in many cases, you can directly translate Sather's logic diagrams to Verilog code. BTW, Sather's book has recently been reissued: https://www.callapple.org/books-3/understanding-the-apple-ii...
Good catch, that's a mistake that's now been corrected, it's definitely 480p. The Github page (https://github.com/a2fpga/a2fpga_core) had it correctly.
Project co-creator here - that's actually the V1 board, the V2 board is here https://github.com/a2fpga/a2fpga_core/blob/main/boards/a2n20... and uses a slightly larger CPLD (complex programmable logic device) which is what's used to map and level shift the 5V signals from the Apple II bus to the 3.3V pins on the FPGA module. We use the Sipeed Tang Nano 20K FPGA module for the FPGA. Using a pre-built module like this is a great accelerator in this type of project because a lot of the more complicated things to get right, like the power supplies or the length of the traces for the HDMI connector, are done for you.
Quick question: my ROM03 IIgs has a Transwarp GS, SCSI card-hard disk and GGlabs 8MB RAM card. Think this would work with that configuration, or would it likely have conflicts?
I have the exact same setup except for the SCSI card and it works with that. The issue will be if the SCSI card is in one of the slots that has been virtualized on the FPGA (4 and 7 by default), in which case there will be address range conflicts. For example, if the SCSI card is in slot 7, then it will conflict with the SuperSprite functionality which uses the address range for Slot 7. There is a "No-Sprite" version of the firmware which disables the SuperSprite or you can move the SCSI card to Slot 3 and put the A2FPGA in Slot 7. ROM03 GS units have the necessary address line signals that the A2FPGA needs on all the slots whereas previous models of the GS only had those on Slot 3.
Echoing some of the comments here, part of this depends on whether you’re using MacOS or not and what else you’re using the monitors for. I use 4K monitors for both Mac and Windows and I stick close to the Apple recommended HiDPI approach which means your 4K display isn’t larger than 24” and your 5K display isn’t larger than 27”. YMMV but most people who have a bad 4K experience are trying to do 4K at 27” or greater. Due to DisplayPort 1.2 bandwidth limitations, the 5K 27” monitor market never got - great range of options. You either have the Thunderbolt-based monitors that are mostly for use in the Mac ecosystem (and only some Mac models) or a few expensive dual-cable DisplayPort 1.2 options or DisplayPort 1.4 options with an assortment of compatibility issues.
I've got one of these and love it and I know a few other developers who do too. The main negatives I've seen are from people who want to stick PC GPU cards in for gaming. As a developer desktop computer it's a joy to use, virtually silent and can power multiple 4K displays. It's a shame Apple hasn't done an update though.
Very well presented. I still have a couple of these in my collection. It's amazing to think about all of these home computer startups that were founded and went bust in the late seventies and early eighties - there's hundreds listed at http://www.old-computers.com/. I'd have loved to see their investor pitches and business plans. I'm sure they all thought they were #2 behind Apple.
Very cool arcticle! I've played around with this sort of thing and at one time had the idea to create a small FPGA board that could be used as a pin-compatible drop-in for either the NES PPU or the TMS9918 but shelved it. The new miniSpartan board is going to be a great board for experimenting with this sort of thing:
would you have done just a straight clone or would you improve the visual output in some way? what sorts of things could you do while retaining pinout compatibility?
HDMI output would have been the main display improvement but given where a PPU or a VDP sits in these architectures, you could do a lot of fun stuff including running your own CPU core on the FPGA. (Edited - thought there was a wait pin from the PPU to the CPU but looks like it's an interrupt)
