I think IBM found that the last level cache in their Power7 CPUs were faster with eDRAM than with SRAM because the reduction in transmission latency enabled by the smaller size made up for the higher cell latency so that's probably the crossover point where cell density wins over reasonable cell latencies. Of course memories with very large latency operations like a Flash erase can still dominate at much large sizes. And for off-die memory the transport is going to mask most differences anyways.
The various sort of stacked memory coming into commercial use have the potential to reduce interconnect power and potentially make active RAM power at least slightly relevant. But I think the interesting thing about reducing RAM power consumption is decreasing passive power. Not that I expect anything to come of it for at least another half decade.
The various sort of stacked memory coming into commercial use have the potential to reduce interconnect power and potentially make active RAM power at least slightly relevant. But I think the interesting thing about reducing RAM power consumption is decreasing passive power. Not that I expect anything to come of it for at least another half decade.