Since ARM has plenty of space in a 32 bit instruction, both the shift and the add are baked into the ldr instruction.

Even in Cortex-M, most array accesses are two instructions (lsls+ldr), as the ldr includes a "free" register+register add. For example, given an index in r0 and an array base address in r3:

    lsls    r0, r0, #2
    ldr     r0, [r0, r3]